1. Field of the Invention
This invention relates to microprocessors, and more particularly, to efficiently performing micro architectural checkpointing.
2. Description of the Relevant Art
Microprocessors typically include overlapping pipeline stages and out-of-order execution of instructions. Additionally, microprocessors may support simultaneous multi-threading and speculative execution to increase throughput. These techniques take advantage of instruction level parallelism (ILP) in source code. However, control dependencies and data dependencies reduce maximum throughput of the microprocessor. In addition, as the speculative instruction window size increases, the penalty for misprediction recovery also increases.
Regarding data dependencies, the data dependencies may appear either between operands of subsequent instructions in a straight line code segment or between operands of instructions belonging to subsequent loop iterations. Register renaming is used to allow parallel execution of instructions despite the WAR and WAW dependencies. However, the true dependency, or RAW dependency, is still intact. Therefore, architectural registers repeatedly used as a destination register and subsequently as a source register cause serialization of instruction execution for associated source code segments.
One example of a common RAW dependency with an architectural register is an assignment performed with a move operation. The move operations may frequently occur within subroutines used to reduce the cost of developing large, reliable programs. Subroutines are often collected into libraries and used for sharing software. Regarding the penalty with misprediction recovery, as the instruction window increases, the penalty to restart and re-execute instructions increases. In addition, maintaining the state of critical resources within the processor may become complex and expensive.
In view of the above, efficient methods and mechanisms for efficiently performing microarchitectural checkpointing are desired.